WP2 Hardware Architecture

Background
A prerequisite for the near future introduction of Integrated Safety Systems is the definition of a vehicle on-board electronic hardware infrastructure that supports in a cost effective manner the very high ISS application demands in terms of dependability, computational power, high speed and accurate information exchange. For hardware infrastructure it is expected that a distributed logic system architecture composed of several Electronic Control Units (ECUs) connected with different communication networks and with a proper ECU internal hardware design will be required. Such hardware architecture must support the different software layers defined in WP1 (Software Architecture).

Main Objectives
Main requirements addressed for this hardware architecture are:

Scalability for standardized usage for safety and non-safety applications
Flexibility to cope with the different application domains and vehicle classes
Architectural simplicity
Capability of handling a large variety of new kinds of sensors and actuators
Support for fault tolerance, error detection and error handling
Well defined and standardized interfaces
Means for functional integration into silicon components
Optimised costs and reliability

Expected Outcome

The work in WP2 is expected to give the following results:

Collection and analysis of the overall requirements concerning a hardware architecture that shall provide a platform for Integrated Safety Systems.
Design guidelines and a general vehicle system architecture framework for composing the future specific ISS applications into high– and low-end vehicles.
Concepts and specifications for the system topology, for the overall communication infrastructure and for the fail operational electronic controls.
A simulation environment for design and configuration of communication systems for integrated safety systems to handle the system complexity.
An electronic control unit prototype with fault tolerance characteristics showing the composability of two fail silent nodes (FSN).

Partners:

Contact:
Centro Ricerche Fiat
Ing. Massimo Osella
Strada Torino 50, 10043 Orbassano (TO),
ITALY

	WP2 Hardware Architecture Background A prerequisite for the near future introduction of Integrated Safety Systems is the definition of a vehicle on-board electronic hardware infrastructure that supports in a cost effective manner the very high ISS application demands in terms of dependability, computational power, high speed and accurate information exchange. For hardware infrastructure it is expected that a distributed logic system architecture composed of several Electronic Control Units (ECUs) connected with different communication networks and with a proper ECU internal hardware design will be required. Such hardware architecture must support the different software layers defined in WP1 (Software Architecture). Main Objectives Main requirements addressed for this hardware architecture are: Scalability for standardized usage for safety and non-safety applications Flexibility to cope with the different application domains and vehicle classes Architectural simplicity Capability of handling a large variety of new kinds of sensors and actuators Support for fault tolerance, error detection and error handling Well defined and standardized interfaces Means for functional integration into silicon components Optimised costs and reliability Expected Outcome The work in WP2 is expected to give the following results: Collection and analysis of the overall requirements concerning a hardware architecture that shall provide a platform for Integrated Safety Systems. Design guidelines and a general vehicle system architecture framework for composing the future specific ISS applications into high– and low-end vehicles. Concepts and specifications for the system topology, for the overall communication infrastructure and for the fail operational electronic controls. A simulation environment for design and configuration of communication systems for integrated safety systems to handle the system complexity. An electronic control unit prototype with fault tolerance characteristics showing the composability of two fail silent nodes (FSN). Partners: Contact: Centro Ricerche Fiat Ing. Massimo Osella Strada Torino 50, 10043 Orbassano (TO), ITALY